The invention relates to charge transfer devices comprising n memory elements, in which the stored charges are transferred by means of two or four clock signals produced by a clock signal generator, the two or four clock signals being applied to each memory element by means of two or four contact areas, at each of which appears a capacitance Ce between adjacent areas and a capacitance Cs between an area and the substrate of the charge transfer device.
The invention further relates to applications of such charge transfer devices, for example for handling digital oscilloscopy signals or for handling pictures. For example, a prior-art CCD system for rapid data recording is shown in U.S. Pat. No. 4,393,357.
A charge transfer device (CTD) is a shift register for analog signals. In its simplest form it is constituted by a monocrystalline semiconductor substrate, on which different electrodes are arranged, which are isolated from the substrate by oxide layers. The substrate generally consists of silicon and the isolating material is silicon oxide. Under each electrode appear charge packets, which are injected by means of an electric contact under the control of a clock signal. The charge transfer device stores the samples of the signal in the form of charge packets and then transfers them generally to a charge amplifier, while holding the charge packets isolated from each other. According to the technologies used, the transfers are effected by means of two, three or four consecutive electrodes for each memory element. Clock signals are applied to these electrodes, the voltage of these signals varying periodically and these signals having two, three or four phases according to the number of electrodes. Thus, potential wells are formed under each electrode, which are translated progressively over the whole line of memory elements producing the machanism of charge transfer from one electrode to the following electrode.
However, a high charge storage capacity has to be ensured and the effects of the surface states have to be reduced. Therefore, the major part of the charge is transferred in a highly doped zone close to the surface under the influence of the self-induced electric field and the remaining part of the charges is transferred in a deeper zone of the crystal having a lower doping under the influence of an external electric field. A peristaltic charge transfer device (PCCD) is then concerned, which may further have an improved transfer efficiency by providing a profiled doping in order to reduce the influence of the surface states. A profiled peristaltic charge transfer device (P.sup.2 CCD) is then obtained. These devices have a transfer efficiency reaching 0.999999 and a maximum clock frequency of 1.5 GHz.
The circuits for generating the four clock signals of a P.sup.2 CCD having four phases therefore have to supply signals having very rapid transitions between the voltage levels, i.e. for the capacitive charges which are important.
These capacitive charges have such values that at frequencies higher than, for example, 100 MHz, great difficulties are involved in obtaining the clock pulse generator, as a result of which the charge transfer devices cannot be used in the proximity of their maximum natural operating frequency.
Such a charge transfer device has been described in the article entitled: "P.sup.2 CCD in 60 MHz oscilloscope with Digital Image Storage" of H. Dollekamp, L. Esser, H. de Jong, Philips Tech. Rev. (1982), Vol. 40, No. 170 , p. 55 to 68. An oscilloscope is described therein which utilizes a charge transfer device in which the sampling and memorization of the imput signal and then the transfer of the required samples to an output member are carried out. This article illustrates that in the case of a charge transfer device of the P.sup.2 CCD type provided with four clock electrodes, the operation of transferring charges can generally not exceed operating frequencies higher than 180 MHz, while the CTD could intrinsically operate at 1.5 GHz - because the circuits for generating the clock signals cannot operate at higher frequencies, taking into account the high capacitive impedances presented by the transport zone of the CTD. This limit of 180 MHz can be slightly improved, but at the expense of a substantial increase of the dissipation of the circuits for generating the clock signals, which is detrimental to the applications themselves.
On the contrary, the generation of fast clock signals for load impedances which are highly resistive does not give rise to great difficulties in the frequency range aimed at.